Advanced PG Diploma in VLSI Design

Module 1 (Front End)

Digital Electronics, STA, VHDL, Verilog, SIMULATION & SYSTHESIS, PLD
Introduction to Digital Systems, difference between digital and analog design, Basic Gates, Combinational logic design, how to design combination logic, Sequential logic, Synchronous & Asynchronous, FSM, Sequential designs, Mealy & Moore machine, Optimization, projects on FSM Language elements, Expressions, Gate level modelling, User defined primitives Blocking & Non-blocking assignments, Timing controls, File IO, Compiler directives, Delay, Data flow, Behavioural, Structural modelling, Tasks, Functions, Race condition, Verification, Test bench design & stimulus, Verliog and VHDL Synthesis, Coding style, PLI. Introductions to timing static and dynamic hazards, path delay, gate delay, metastability states. Sequential timing delays like set-up time, hold time, maximum frequency, violations, slew, slack. Delay analysis w.r.t. Sequential logic pad to set up, pad to pad, clk to next Reg, Reg to o/p and Reg to Reg. violations wrt sequential circuit. Why synthesis? Synthesis flow-optimization techniques, Verilog syntheses, Synthesis Tips, Guidelines, Pipelining, Register Balancing.

Module 2 ( Verification)

System Verilog, Perl

Traditional verification approaches and issues related to it, The Verilog solution, Introduction to Coverage Driven Verification (CDV) methodology. Classes, Properties, dmethods, Constructors, Data hiding, Encapsulation, Polymorphism, Inheritance, Constrained-Random Generation, Random variables, The randomize () Function, Defining constraints. Coverage & assertions with tool related Scripting language PERL.

Module 3 (Back End)

ASIC Flow and Testing

Basics of CMOS includes - what is transistor, transistor acting as switch- basic designs like gates, muxes transmission gates, standard cell design in layout, verifying DRC-LVS-RC extraction-finally simulating the design to check functionality. ASIC - after the Logic synthesis, Power, Timing, design, & area constraints - netlist is obtained physical design includes, partioning of the design, floor planning- placement, STA (Static Timing analysis) Behavioural synthesis, Formal Verification, clock tree synthesis-DFT-ATPG test pattern generation-scan insertion boundary scan-BIST(built in self test), power grid placement, I/O placement, standard cell placement, power consumption and analysis, global and detailed routing, Clock & Test insertion-final conversion to GDSII or EDIF format.

Course Duration

The Course duration is 396 hrs. - 99 Working Days (inclusive of Project)

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