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   VLSI Design

Why VLSI Design?

To improve the infrastructure for VLSI further to achieve greater productivity and efficiency, there is a great surge in demand for people with expertise in this field. With this demand, the opportunities in the VLSI domain have multiplied in the recent past necessitating thrust on grooming industry ready professionals. There are tremendous opportunities to work and to grow in the field of VLSI Design.

This is truly a sunrise industry.

 

Objective

The main objective of the course is to provide a comprehensive and state of the art knowledge in the area of VLSI Design.

The course emphasis is on the structure and function of the complete system. A detailed study of the subsystems that comprises the overall system is carried out.

 

The technical knowledge provided in the course on different aspects of the system will help the participant in understanding the functioning of the system. This will further help in providing the necessary expertise required by the industry.

 

Eligibility

B.E. / B.Tech in Electronics, Computer Science, Instrumentations and Electrical Engineering discipline with a minimum of 60% aggregate. Final year students with good Academic track record can also apply.

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Certificate Course in VLSI Design

 

Module 1 (Front End)

Digital Electronics, STA, VHDL, Verilog, SIMULATION & SYSTHESIS, PLD
Introduction to Digital Systems, difference between digital and analog design, Basic Gates, Combinational logic design, how to design combination logic, Sequential logic, Synchronous & Asynchronous, FSM, Sequential designs, Mealy & Moore machine, Optimization, projects on FSM Language elements, Expressions, Gate level modeling, User defined primitives Blocking & Non-blocking assignments, Timing controls, File IO, Compiler directives, Delay, Data flow, Behavioral, Structural modelling, Tasks, Functions, Race condition, Verification, Test bench design & stimulus, Verliog and VHDL Synthesis, Coding style, PLI. Introductions to timing static and dynamic hazards, path delay, gate delay, metastability states. Sequential timing delays like set-up time, hold time, maximum frequency, violations, slew, slack. Delay analysis w.r.t. Sequential logic pad to set up, pad to pad, clk to next Reg, Reg to o/p and Reg to Reg. violations wrt sequential circuit. Why synthesis? Synthesis flow-optimization techniques, Verilog syntheses, Synthesis Tips, Guidelines, Pipelining, Register Balancing.

 

Module 2 ( Verification)

System Verilog, Perl

Traditional verification approaches and issues related to it, The Verilog solution, Introduction to Coverage Driven Verification (CDV) methodology. Classes, Properties, dmethods, Constructors, Data hiding, Encapsulation, Polymorphism, Inheritance, Constrained-Random Generation, Random variables, The randomize () Function, Defining constraints. Coverage & assertions with tool related Scripting language PERL.

 

Course Duration

The Course duration is 240 hrs. - 60 Working Days (inclusive of Project)

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