Altera has appointed UTL Technologies as their authorized training partner for training their customers on Altera products across India. This training is also extended to universities and colleges to create awareness among the students and the faculty members about the latest tools and technology from Altera. This privilege is accorded to UTL by virtue of its contribution to the Semiconductor industry in terms of technology training an trained manpower.

About Altera

Altera was founded in 1983 by Robert Hartmann, Michael Magranet, Paul Newhagen, and Jim Sansbury, visionaries who capitalized on the research of the day, stating that semiconductor customers would benefit from a user-programmable standard product alternative to gate arrays. To address these market needs, Altera's founders pioneered the first programmable logic device (PLD), the EP300, giving birth to an entirely new market segment in semiconductors. This new, flexible solution beat traditional standard products to market and launched Altera's reputation as a semiconductor innovation leader.

Training Programs Offered…   

1. Accelerating Software Using the Nios II C2H Compiler                 

2. Advanced VHDL Design Techniques                                            

3. Advanced Verilog Design Techniques                                         

4. Basic Quartus II Software Tcl Scripting Part 1 of 2          

5. Basic Quartus II Software Tcl Scripting Part 2 of 2                      

6. The Quartus II Software Design Series: Foundation                     

7. The Quartus II Software Design Series: Optimization                  

8. Designing with the Nios II processor and SOPC builder                 

9. Developing software for the Nios II Processor      

10. Implementing DSP Designs in FPGA                                            

11. Developing Software for the Nios II Processor                

12. Developing Software for the Nios II Processor: C2H Fundamentals                            

13. Developing Software for the Nios II Processor: Debug Primer      

14. Developing Software for the Nios II Processor: Design Flow         

15. Developing Software for the Nios II Processor: HAL Primer         

16. Developing Software for the Nios II Processor: Software Build Flow (Part 1)               

17. Developing Software for the Nios II Processor: Software Build Flow (Part 2)               

18. Developing Software for the Nios II Processor: Tools Overview    

19. Early Pin Planning with Pin Planner in the Quartus II Software     

20. FPGA to Board Design Flow Using Mentor Graphics Tools

Training Calendar for - Current Fiscal

Calendar for Feb 08

Calendar for Mar 08